? semiconductor components industries, llc, 2013 may, 2013 ? rev. p2 1 publication order number: tcp ? 3056h/d TCP-3056H advance information 5.6 pf passive tunable integrated circuits (ptic) introduction on semiconductor?s ptics have excellent rf performance and power consumption, making them suitable for any mobile handset or radio application. the fundamental building block of our ptic product line is a tunable material called parascan , based on barium strontium titanate (bst). ptics have the ability to change their capacitance from a supplied bias voltage generated by the control ic. the 5.6 pf ptics are available as wafer-level chip scale packages (wlcsp) and in qfn packages for easy mounting directly on printed circuit boards. key features ? high tuning range and operation up to 20 v ? usable frequency range: from 700 mhz to 2.7 ghz ? high quality factor (q) for low loss ? high power handling capability ? compatible with ptic control ic tcc-103 ? wlcsp package: 0.722 x 1.179 x 0.611 mm (12 pillar) ? qfn package: 1.200 x 1.600 x 0.950 mm ? qfn: msl ? 2 moisture sensitivity level (per j ? std ? 020) ? pb ? free and rohs compliant typical applications ? multi-band, multi-standard, advanced and simple mobile phones ? tunable antenna matching networks ? tunable rf filters ? active antennas this document contains information on a new product. specifications and information herein are subject to change without notice. device package shipping ordering information http://onsemi.com tcp ? 3056h ? dt wlcsp (pb ? free) 4000 units / 7? reel wlcsp 12 pillar case tbd qfn 6 pin case tbd for detailed ordering information, including part number definition and capacitance (pf) see the package dimensions section on page 7 of this datasheet. tcp ? 3056h ? qt qfn (pb ? free) 8000 units / 13? reel functional block diagram figure 1. ptic functional block diagram qfn marking diagram x.x = 5.6 h = high tuning ptic bias rf1 rf2 x.xh
tcp ? 3056h http://onsemi.com 2 typical specifications representative performance data at 25 c table 1. performance data parameter min typ max units operating bias voltage 2.0 20 v capacitance (v bias = 2 v) 5.04 5.60 6.16 pf capacitance (v bias = 20 v) 1.40 1.47 1.55 pf tuning range (2 v - 20 v) 3.40 3.80 4.20 tuning range (20 v - 2 v) 3.60 leakage current (wlcsp) 2.0 a operating frequency 700 2700 mhz quality factor @ 700 mhz, 10 v 100 quality factor @ 2.4 ghz, 10 v 65 ip3 (v bias = 2 v) [1,3] 70 dbm ip3 (v bias = 20 v) [1,3] 85 dbm 2nd harmonic (v bias = 2 v) [2,3] ? 70 dbm 2nd harmonic (v bias = 20 v) [2,3] ? 80 dbm 3rd harmonic (v bias = 2 v) [2,3] ? 40 dbm 3rd harmonic (v bias = 20 v) [2,3] ? 70 dbm transition time (cmin cmax) [4] 80 s transition time (cmax cmin) [4] 70 s 1. f 1 = 850 mhz, f 2 = 860 mhz, pin 25 dbm/tone 2. 850 mhz, pin +34 dbm 3. ip3 and harmonics are measured in the shunt configuration in a 50 environment 4. rf in and rf out are both connected to dc ground
tcp ? 3056h http://onsemi.com 3 representative performance data at 25 c for 5.6 pf wlcsp package figure 2. capacitance figure 3. harmonic power* figure 4. ip3* figure 5. q* *the data shown is based on the tcp ? 1056n device performance, for reference only. the tcp ? 3056h performance data will be available in the production datasheet. table 2. absolute maximum ratings parameter rating units input power +40 dbm bias voltage +25 (note 5) v operating temperature range ? 30 to +85 c storage temperature range ? 55 to +125 c esd ? human body model class 1a jedec hbm standard (note 6) stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 5. wlcsp: recommended bias voltage not to exceed 20 v 6. class 1a defined as passing 250 v, but may fail after exposure to 500 v esd pulse
tcp ? 3056h http://onsemi.com 4 package information qfn package layout and dimensional information figure 6. qfn pin markers and dimensions top view (note: x.x reflects the ptic value e.g.: 5.6 indicates 5.6 pf) side view top view (seen through package) metal pads far side recommended pcb pad layout for 6 pin package (metal defined pads) recommended pcb pad layout for 6 pin package (solder mask defined pads) 1.200 mm 0.050 mm 1.600 mm 0.050 mm x.xh 0.950 mm 0.050 mm 0.000 mm / 0.050 mm bias rf2 rf1 n/c rf2 rf1 3x 0.250 mm 3x 0.700 mm 2x 0.300 mm 4x 0.500 mm 4x 0.175 mm 6x 0.075 mm 6x 0.250 mm 0.030 mm 6x 0.350 mm 0.030 mm pin #1 id 0.100 x 45 chamfer bias rf2 rf1 n/c rf2 rf1 bias rf2 rf1 n/c rf2 rf1 3x 0.200 mm 6x 0.575 mm 0.475 mm 6x 0.400 mm 6x 0.300 mm 4x 0.100 mm 6x pcb top solder mask opening 4x pcb top metal 2x 0.100 mm 2x 0.900 mm 4x 0.575 mm 4x 0.475 mm 6x 0.300 mm 2x 0.400 mm 2x 0.200 mm 6x pcb top solder mask opening 4x pcb top metal note: 2x means 2 sites with the specific value 3x means 3 sites with the specific value 4x means 4 sites with the specific value 0.9 mm pad layout is standard for all products. shorter pad layouts can be considered for smaller products.
tcp ? 3056h http://onsemi.com 5 wafer level chip scale package (wlcsp) layout and dimensional information figure 7. wlcsp pin markers and dimensions a2 d1 c2 2x 0.104 mm (typ) (copper pillar) 2x 0.069 mm (typ) (copper pillar) rf pillars 0.104 mm (typ) rf pillars 0.069 mm (typ) c1 a1 b3 c3 bottom view (pillars up) side view b1 b4 d2 top view (pillars down) note: 2x means 2 sites with the specific value 3x means 3 sites with the specific value 4x means 4 sites with the specific value d3 (copper pillar height) b2 rf1 rf2 b2 rf1 rf2 rf1 rf2 rf1 rf2 rf1 rf2 n/c bias table 3. package dimensions (all dimensions are in millimeters) wlcsp * dim nominal max device 8p a1 0.879 1.2, 2.7 pf 10p a1 1.029 3.3, 3.9 pf 12p a1 1.179 4.7, 5.6, 6.8, 8.2 pf 14p a1 1.329 all a2 0.722 all b1 0.460 all b2 0.150 all b3 0.300 all b4 0.130 all c1 0.148 all c2 0.425 all c3 0.130 all d1 0.530 all d2 0.081 *total number of pillars figure 8. recommended pad layout note: 0.9 mm pad layout is standard for all products. shorter pad layouts can be considered for smaller products.
tcp ? 3056h http://onsemi.com 6 assembly considerations and reflow profile the following assembly considerations should be observed: cleanliness these chips should be handled in a clean environment . electro-static sensitivity on semiconductor?s ptics are esd class 1a sensitive. the proper esd handling procedures should be used. mounting the wlcsp ptic is fabricated for flip chip solder mounting. connectivity to the rf and bias terminations on the ptic die is established through copper pillar posts (53 m nominal height) topped with lead-free sac351 solder caps (28 m nominal height). the ptic die is rohs-compliant and compatible with lead-free soldering profile. post-reflow cleaning use of ultrasonic cleaning is not recommended for pillared devices as it may lead to premature fatigue failure of the pillars. molding the ptic die is compatible for over-molding or under-fill. figure 9. reflow profile orientation of the ptic for optimum losses when configuring the ptic in your specific circuit design, at least one of the rf terminals must be connected to dc ground. if minimum transition times are required, dc ground on both rf terminals is recommended. to minimize losses, the ptic should be oriented such that rf2 is at the lower rf impedance of the two rf nodes. a shunt ptic, for example, should have rf2 connected to rf ground. figure 10. ptic orientation functional block diagram bias rf ant rf1 (ptic pad) rf2 (ptic pad)
tcp ? 3056h http://onsemi.com 7 part number definition example: tcp ? 3056h ? dt tcp - 30 56 h - d t - - product family tcp capacitor value process generation process status ?blank? = production x = pilot production s = special/custom p = prototype package / format d = wlcsp q = qfn packing tuning n = normal h = high 10 = gen 1.0 30 = gen 3.0 12 = 1.2 pf 27 = 2.7 pf 33 = 3.3 pf 39 = 3.9 pf 47 = 4.7 pf 56 = 5.6 pf 68 = 6.8 pf 82 = 8.2 pf t = t&r table 4. part numbers part number capacitance package* 2 v 20 v TCP-3056H-dt 5.60 1.43 12-pillar wlcsp TCP-3056H-qt 5.60 1.43 6-pin qfn *see ptic package dimensions on page 5
tcp ? 3056h http://onsemi.com 8 tape & reel dimensions figure 11. 12 pillar wlcsp carrier tape drawing 4.00 0.10 4.00 0.10 8.00 + 0.30 ? 0.10 2.00 0.05 ? 1.50 + 0.10 1.75 0.10 3.50 0.05 45 0.82 0.05 a o 1.28 0.05 b o 0.20 0.02 0.76 0.05 k o 0.20 0 45 0 note: the reel size is 7? pocket may have a hole 0.2 mm to 0.4 mm 0.05 mm
tcp ? 3056h http://onsemi.com 9 tape & reel dimensions (cont?d) figure 12. qfn carrier tape drawing 4.00 0.10 4.00 0.10 8.00 + 0.30 ? 0.10 2.00 0.05 ? 1.50 + 0.10 1.75 0.10 3.50 0.05 ? 0.60 0.05 5 max 1.32 0.05 a o 5 max 1.82 0.05 b o 0.25 0.02 1.10 0.05 k o pin 1 (upper left) table 5. pocket dimension pocket dimension (mm) unit dimension (mm) spec max min spec max min ao 1.32 0.05 1.37 1.27 a 1.2 0.05 1.25 1.15 bo 1.82 0.05 1.87 1.77 b 1.6 0.05 1.65 1.55 ko 1.1 0.05 1.15 1.05 k 0.95 0.05 1.00 0.90 note: the reel size is 13? on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 tcp ? 3056h/d parascan is a trademark of paratek microwave, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
